Monday, December 7, 2009

On the Selection of Power Delivery Network in SoCs

The design and selection of a SoC power delivery network (PDN) presents unique challenges and its design is critical to achieving power consumption goals of the design. This is true when your PDN is external and based on off-the-shelf components as well as when it is being designed on-chip as part of the SoC. This article explores the external situation.

Power architecture of a given power-managed design determines various power modes of that design. Each power mode implies a set of power supply voltages and load current requirements for the PDN. These requirements drive the selection of voltage regulator modules (VRM) that supply the design with appropriate voltage and current levels in different power modes of the design. This process is a lot more challenging that it appears to be.

To begin with, you have the task of establishing target impedances to be met across a range of frequency values for the PDN and then of designing in appropriate decoupling capacitors to meet impedance goals. This is a challenging process in itself but addresses only part of the problem. The selection of appropriate VRMs to supply the design can be equally challenging. Here are some of the factors to consider:

• There are a large number of regulator suppliers such as Texas Instruments, National Semiconductor, Linear Technology, and Analog Devices to name a few.
• The PDN designer needs to carefully look into the switching and linear types of regulators to meet power efficiency and current goals.
• Input and output voltage as well as load current requirements are some of constraints to limit your search
• Power efficiency and consumption goals for the design under consideration must be met.
• Cost of the design places a limit on cost of regulators.
• You can potentially use a hierarchy of regulators to meet these goals.

All of these requirements and given a large number of choices to begin with make this task a challenging one. And it can get more complex when if you bring variable voltages into the picture. It is critical that PDN is done right because an efficient PDN is equivalent to saving a lot effort in optimizing power of the design and the job done well can give you a clear edge in time-to-market with your low power device.

Wednesday, November 11, 2009

Is Power-Aware Simulation a Must-Have?

"Power-Aware Simulation" here refers to power-aware simulation-based verification. This question has been frequently asked by the designers and becomes an even more important one in the context of potentially increased cost of simulation, with or without recessionary environment.

Those contending that it is not a must-have point to:

• Power-managed designs were being done even when there was no power-aware simulation. The use of rule-based checking addressed most of power related issues and could be custom developed for a design methodology.

• The use of power format brings in a new variable and associated design methodology challenges.

• You could modify the design in a way to see the effects of power shutdowns in a regular simulation context.

• You could modify the design library for simulation to include the effects of power shutdowns. For example, the simulation definition of an AND gate would also include the supply variable VCC and could model the AND gate using the following table: (X implies a 0 or a 1, and Z means a floating value)
A | B | VCC | OUT
1 | 1 | 1 | 1
0 | X | 1 | 0
X | 0 | 1 | 0
X | X | 0 | Z

All of these are valid points but there are some significant issues that are not addressed by these solutions and there are some significant issues which are created by using these solutions. Here are some points for using power-aware simulation:

• There are several power management issues that can only be validated over a few simulation cycles and static checking of the design will not be sufficient. Some of these may indeed get addressed through the use of formal techniques. Ensuring that the proper sequencing of clock gating, power shutdown, isolation, reset and retention occurs is an example pointing to the need of a dynamic method.

• One would like validate a design early in the design cycle and not wait until gate-level simulation. This is an argument against the use of modified library for power-aware simulation. Simulations are lot slower at gate-level leading to higher costs and issues found later in the design cycle will end up costing a lot more through delays in TTM.

• Validations via design modification are effective but introduce another source of error and extra design version management costs. When you are dealing with designs with several power domains, it becomes quickly unmanageable.

• While there are issues related to the use of newly created power formats (i.e., IEEE p1801), it is much better to capture power intent once to coordinate various design tasks. Not only different tools will have a single view of intent, the verification needs to be carried out at various levels of abstraction can now be driven by the same intent.

There is a clear need for power-aware simulation in power-managed designs. While techniques based on design and/or library modifications can do the job, there is an indirect cost to using such methodologies. As power-aware simulation becomes a more mature technology and power-management of designs continue to get more complex, power-aware simulation will become a must-have starting point for chip design creation.

Thursday, October 15, 2009

On DeCap Verification in Power Gated Designs

A decoupling capacitor (DeCap) is used in power managed designs to decouple a power domain from the effects of power switching in a related domain.

A switching sub-circuit (a power domain or a voltage island) can mess up the power supply line upon which other sub-circuits or domains depend upon. When a load switches into a circuit, the circuit tries to increase its current draw but the inductance associated with power supply line will act against this change. This change is opposed by lowering of the voltage the power supply line provides. This voltage may be powering other domains which may malfunction because of the drop. All domains that depend on this power supply line will get affected. The changes are temporary since the inductance eventually loses the battle but these changes may cause the design to malfunction.

A DeCap connected to the supply power line helps decouple other domains from these sudden changes by stabilizing the supply needs through its stored charge. When the load is switched out, the DeCap is charged and becomes ready to supply when supply line balks at supplying during the switching in of a new load. By the time DeCap discharges, the main supply should be stabilized. A careful analysis of load requirements goes into the design of DeCaps.

Power managed designs require a host of structural verification checks to ensure appropriate level shifters, isolators, and retention cells are present in the design along with correct power connectivity to various domains and specials cells. Ensuring presence of DeCaps is another one of these checks that help ensure presence of appropriate protection for the load switching events in the low power designs that typically contain several power modes as appropriate for different applications. And just like other structural checks, it can help avoid a potential re-spin of the design.

Wednesday, September 16, 2009

Strategies for Power Management Verification

In an earlier blog article, we took a look at some of the top power management verification issues. Typical power management verification strategy requires a combination of structural rule-checking, power-aware simulation, and formal validation to address these issues.

In the previous blog article, we discussed the need for power-aware simulation and stressed the fact you have to orchestrate your verification strategy to use structural and formal checking tools to optimize the extent of dynamic simulation needed. In this article, we list various verification strategies for the top verification issues discussed in an earlier article.

In the table listed below, verification strategies are listed as simulation, formal, and structural rule-checking. The notation used here is that “1” implies that the corresponding verification strategy is typically the main strategy for dealing with the issue and “2” being the secondary strategy complementing the main strategy.















































































Verification Issue Simulation Formal Structural
Reset on Wake Up 1 2*
Power Connectivity 2# 1
Always-on Buffers 1
Domain Isolation 1 2
Power Switching 1$
Power Controller 1 2
Level Shifting 1
Power Sequencing 2 1%
State Retention 1 2
Decaps 1



Table 1: Verification Issues and Strategies


Notes:

*You can use structural techniques to ensure that proper reset signals are present in the registers for domain under considerations but nothing better than ensuring the reset sequence occurred correctly upon wake up via power-aware simulations.

#You can simulate power connectivity issues if you have power-aware models of cells in the design and have a power-connected netlist. In absence of such a methodology, structural checking to ensure proper connectivity is the only way out. This is a big issue in multi-voltage design and frequent cause of re-spins.

$This is usually done in conjunction with the power connectivity checking to ensure correct power switched signals are reaching their intended destinations.

%Formal is the most secure way of validating properties of power sequencing but this can also be validated via power-aware simulations.

There are other power management verification issues depending upon how you have been bitten in the past but the above mentioned issues generally figure in most low power design verification list. And a coordinated verification strategy involving power-aware simulation, rule-based structural checking, and formal tools is required in your power management verification methodology.

Wednesday, August 19, 2009

Extent of Dynamic Simulation in Power Management Verification

In the previous blog article, we took a look at some of the main power management verification issues encountered in low power designs. Typical power management verification strategy requires a combination of structural rule-checking, power-aware simulation, and formal validation to address these issues.

One question that comes up very frequently is that of how much more simulation is needed for a design that is power-managed compared to a version of the same design did not incorporate power management. While it is not possible to quantify the answer, we can look into some of the key factors that help guide the strategy for power management verification.

Before we get to the issue of extent of dynamic simulation, we can first discuss if any power management specific simulation is needed at all. While there are a lot of power management issues that can be statically checked, there is no substitute for simulation in dealing with a number of power management issues.

According to Ryan Pinto of Intel, “In any power management design effort, there is no substitute for dynamic simulation. The inherent "real system" nature of such simulations is the only way to demonstrate the actual interactions between logic elements in different power states, as well as the effects of time spatiality in signal transitions due to either variable voltage ramp rates or other sequential logic elements.”

There are some verification issues whose nature is such that they can be validated only dynamically. Power sequencing protocol which determines timings of power switching, clock gating, isolation, and retention can only be validated in a dynamic context. Some aspects of this problem can also be channeled to formal validation.

As you cycle power through a domain multiple times during the course of operation, whether power-on-reset happened correctly each time which correct loading of registers is a classic simulation issue that needs to be power aware now.

The extent of power-aware simulation needed depends a lot on your power management architecture itself and its complexity. You need to be able to validate the design in its possible power states (a combination of on, off, retained, and various states of on due to variable voltages) and, more importantly, in various transitions among these states.

All of this requires validation of existing test cases in different power states and they add new test cases to address power specific issues. You have to carefully look into the differences that power management brings to efficiently upgrade you test environment for validation.

Some power related design properties lay themselves very well to formal checking but you may require help of a power architecure expert to write these assertions for formal tools. Dr. John Goodenough, Director of Design Technology at ARM, when talking about (at DesignCon 2009) an advanced ARM media chip that has “10s” of different domains that can be turned off to save power, recommended experimenting with formal techniques on the Power Controller.

And as you do that, you have to orchestrate your verification strategy to use structural and formal checking tools to optimize the extent of dynamic simulation needed. Power-aware simulation bring in additional test cases, running of existing test cases in different power modes, require potential extensions to your existing test environment for addressing power related issues, and careful thinking of your overall verification strategy. While it is difficult to quantify how much additional simulation is needed in general, it is important to focus on efficiently carrying out whatever that additional simulation amounts to eliminate sources of possible re-spins.

Friday, June 26, 2009

Top Power Management Verification Issues

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Voltage is the strongest handle for managing chip power consumption. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.

We take a look at some of the main power management verification issues based on what I have heard from various design groups using these techniques. Here are what I consider to be the “Top 10” power management verification issues, not in any order though:

1. Reset out of wake up: Since different parts of design are awake in different modes of operation, managing reset out of power up is more complex and must be diligently managed.
2. Power Connectivity: Now that you have several power supply signals connecting different parts of the design, you must ensure supply correctly reaches its designated destination only.
3. Always-on Buffers: Some signals in a power managed designs must be always-on and ensuring always-on buffers associated with those signals is a must.
4. Power Domain Isolation: The switching of power implies domains outputs must be isolated properly; also, inputs depending upon the design methodology.
5. Power Switching Management: Ensuring correct enables to power switches and chaining of power switches to control amount of logic waking up in power sequence is necessary.
6. Power Controller Design: Power state controller must ensure correct signaling for domain switching, isolation, retention etc. based on the power management architecture needs.
7. Level-shifting: Signals that cross voltage domain boundaries need to appropriately level-shifted, and sometimes level-shifted and isolated, on all domain crossings.
8. Power Sequencing Protocol: Power on/off, isolation, retention, clock gating, and voltage changes must follow a signaling protocol to ensure proper working of the design.
9. State Retention: If retention is used with power gating, it is necessary to ensure correct retention upon wake-up whether using state retention power gating registers or save-and-restore via memory.
10. Decap: As multiple power domains are created, ensuring that correct decap cells have been used and connected is necessary.

There are other power management verification issues and depending upon how you have been bitten in the past, they may make your top 10 list. It will be good to hear your experiences with these.

Thursday, May 28, 2009

Power-Aware Verification: Is it a front-end or a back-end issue?

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. Power management techniques that leverage voltage as a handle are bring extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.

There are some significant new challenges in validation of designs using above mentioned techniques as new power states are created in the design. At physical level, dealing with multiple power supplies and variable power supplies present us with many new verification challenges. Can all of the power issues be addressed at the front-end in the context of simulation-based and formal validation techniques? Or is it unrealistic to even think that any true verification is possible without taking back-end into account? Or is this just one of those over-hyped problems? Some of the largest volume consumer electronic products are using these techniques and how are the companies designing these chips are getting them working in these products? How is power management of multi-core and many-core systems getting validated today?

Power-aware validation is a major concern for designs that are leveraging leading edge power management techniques and if you are working through the challenges, I would love to hear your experiences.