In the previous blog article, we took a look at some of the main power management verification issues encountered in low power designs. Typical power management verification strategy requires a combination of structural rule-checking, power-aware simulation, and formal validation to address these issues.
One question that comes up very frequently is that of how much more simulation is needed for a design that is power-managed compared to a version of the same design did not incorporate power management. While it is not possible to quantify the answer, we can look into some of the key factors that help guide the strategy for power management verification.
Before we get to the issue of extent of dynamic simulation, we can first discuss if any power management specific simulation is needed at all. While there are a lot of power management issues that can be statically checked, there is no substitute for simulation in dealing with a number of power management issues.
According to Ryan Pinto of Intel, “In any power management design effort, there is no substitute for dynamic simulation. The inherent "real system" nature of such simulations is the only way to demonstrate the actual interactions between logic elements in different power states, as well as the effects of time spatiality in signal transitions due to either variable voltage ramp rates or other sequential logic elements.”
There are some verification issues whose nature is such that they can be validated only dynamically. Power sequencing protocol which determines timings of power switching, clock gating, isolation, and retention can only be validated in a dynamic context. Some aspects of this problem can also be channeled to formal validation.
As you cycle power through a domain multiple times during the course of operation, whether power-on-reset happened correctly each time which correct loading of registers is a classic simulation issue that needs to be power aware now.
The extent of power-aware simulation needed depends a lot on your power management architecture itself and its complexity. You need to be able to validate the design in its possible power states (a combination of on, off, retained, and various states of on due to variable voltages) and, more importantly, in various transitions among these states.
All of this requires validation of existing test cases in different power states and they add new test cases to address power specific issues. You have to carefully look into the differences that power management brings to efficiently upgrade you test environment for validation.
Some power related design properties lay themselves very well to formal checking but you may require help of a power architecure expert to write these assertions for formal tools. Dr. John Goodenough, Director of Design Technology at ARM, when talking about (at DesignCon 2009) an advanced ARM media chip that has “10s” of different domains that can be turned off to save power, recommended experimenting with formal techniques on the Power Controller.
And as you do that, you have to orchestrate your verification strategy to use structural and formal checking tools to optimize the extent of dynamic simulation needed. Power-aware simulation bring in additional test cases, running of existing test cases in different power modes, require potential extensions to your existing test environment for addressing power related issues, and careful thinking of your overall verification strategy. While it is difficult to quantify how much additional simulation is needed in general, it is important to focus on efficiently carrying out whatever that additional simulation amounts to eliminate sources of possible re-spins.