In the previous blog article, we took a look at some of the main power management verification issues encountered in low power designs. Typical power management verification strategy requires a combination of structural rule-checking, power-aware simulation, and formal validation to address these issues.
One question that comes up very frequently is that of how much more simulation is needed for a design that is power-managed compared to a version of the same design did not incorporate power management. While it is not possible to quantify the answer, we can look into some of the key factors that help guide the strategy for power management verification.
Before we get to the issue of extent of dynamic simulation, we can first discuss if any power management specific simulation is needed at all. While there are a lot of power management issues that can be statically checked, there is no substitute for simulation in dealing with a number of power management issues.
According to Ryan Pinto of Intel, “In any power management design effort, there is no substitute for dynamic simulation. The inherent "real system" nature of such simulations is the only way to demonstrate the actual interactions between logic elements in different power states, as well as the effects of time spatiality in signal transitions due to either variable voltage ramp rates or other sequential logic elements.”
There are some verification issues whose nature is such that they can be validated only dynamically. Power sequencing protocol which determines timings of power switching, clock gating, isolation, and retention can only be validated in a dynamic context. Some aspects of this problem can also be channeled to formal validation.
As you cycle power through a domain multiple times during the course of operation, whether power-on-reset happened correctly each time which correct loading of registers is a classic simulation issue that needs to be power aware now.
The extent of power-aware simulation needed depends a lot on your power management architecture itself and its complexity. You need to be able to validate the design in its possible power states (a combination of on, off, retained, and various states of on due to variable voltages) and, more importantly, in various transitions among these states.
All of this requires validation of existing test cases in different power states and they add new test cases to address power specific issues. You have to carefully look into the differences that power management brings to efficiently upgrade you test environment for validation.
Some power related design properties lay themselves very well to formal checking but you may require help of a power architecure expert to write these assertions for formal tools. Dr. John Goodenough, Director of Design Technology at ARM, when talking about (at DesignCon 2009) an advanced ARM media chip that has “10s” of different domains that can be turned off to save power, recommended experimenting with formal techniques on the Power Controller.
And as you do that, you have to orchestrate your verification strategy to use structural and formal checking tools to optimize the extent of dynamic simulation needed. Power-aware simulation bring in additional test cases, running of existing test cases in different power modes, require potential extensions to your existing test environment for addressing power related issues, and careful thinking of your overall verification strategy. While it is difficult to quantify how much additional simulation is needed in general, it is important to focus on efficiently carrying out whatever that additional simulation amounts to eliminate sources of possible re-spins.
Wednesday, August 19, 2009
Friday, June 26, 2009
Top Power Management Verification Issues
We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.
Voltage is the strongest handle for managing chip power consumption. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.
We take a look at some of the main power management verification issues based on what I have heard from various design groups using these techniques. Here are what I consider to be the “Top 10” power management verification issues, not in any order though:
1. Reset out of wake up: Since different parts of design are awake in different modes of operation, managing reset out of power up is more complex and must be diligently managed.
2. Power Connectivity: Now that you have several power supply signals connecting different parts of the design, you must ensure supply correctly reaches its designated destination only.
3. Always-on Buffers: Some signals in a power managed designs must be always-on and ensuring always-on buffers associated with those signals is a must.
4. Power Domain Isolation: The switching of power implies domains outputs must be isolated properly; also, inputs depending upon the design methodology.
5. Power Switching Management: Ensuring correct enables to power switches and chaining of power switches to control amount of logic waking up in power sequence is necessary.
6. Power Controller Design: Power state controller must ensure correct signaling for domain switching, isolation, retention etc. based on the power management architecture needs.
7. Level-shifting: Signals that cross voltage domain boundaries need to appropriately level-shifted, and sometimes level-shifted and isolated, on all domain crossings.
8. Power Sequencing Protocol: Power on/off, isolation, retention, clock gating, and voltage changes must follow a signaling protocol to ensure proper working of the design.
9. State Retention: If retention is used with power gating, it is necessary to ensure correct retention upon wake-up whether using state retention power gating registers or save-and-restore via memory.
10. Decap: As multiple power domains are created, ensuring that correct decap cells have been used and connected is necessary.
There are other power management verification issues and depending upon how you have been bitten in the past, they may make your top 10 list. It will be good to hear your experiences with these.
Voltage is the strongest handle for managing chip power consumption. Power management techniques that leverage voltage as a handle are being extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.
We take a look at some of the main power management verification issues based on what I have heard from various design groups using these techniques. Here are what I consider to be the “Top 10” power management verification issues, not in any order though:
1. Reset out of wake up: Since different parts of design are awake in different modes of operation, managing reset out of power up is more complex and must be diligently managed.
2. Power Connectivity: Now that you have several power supply signals connecting different parts of the design, you must ensure supply correctly reaches its designated destination only.
3. Always-on Buffers: Some signals in a power managed designs must be always-on and ensuring always-on buffers associated with those signals is a must.
4. Power Domain Isolation: The switching of power implies domains outputs must be isolated properly; also, inputs depending upon the design methodology.
5. Power Switching Management: Ensuring correct enables to power switches and chaining of power switches to control amount of logic waking up in power sequence is necessary.
6. Power Controller Design: Power state controller must ensure correct signaling for domain switching, isolation, retention etc. based on the power management architecture needs.
7. Level-shifting: Signals that cross voltage domain boundaries need to appropriately level-shifted, and sometimes level-shifted and isolated, on all domain crossings.
8. Power Sequencing Protocol: Power on/off, isolation, retention, clock gating, and voltage changes must follow a signaling protocol to ensure proper working of the design.
9. State Retention: If retention is used with power gating, it is necessary to ensure correct retention upon wake-up whether using state retention power gating registers or save-and-restore via memory.
10. Decap: As multiple power domains are created, ensuring that correct decap cells have been used and connected is necessary.
There are other power management verification issues and depending upon how you have been bitten in the past, they may make your top 10 list. It will be good to hear your experiences with these.
Thursday, May 28, 2009
Power-Aware Verification: Is it a front-end or a back-end issue?
We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi-core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.
Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. Power management techniques that leverage voltage as a handle are bring extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.
There are some significant new challenges in validation of designs using above mentioned techniques as new power states are created in the design. At physical level, dealing with multiple power supplies and variable power supplies present us with many new verification challenges. Can all of the power issues be addressed at the front-end in the context of simulation-based and formal validation techniques? Or is it unrealistic to even think that any true verification is possible without taking back-end into account? Or is this just one of those over-hyped problems? Some of the largest volume consumer electronic products are using these techniques and how are the companies designing these chips are getting them working in these products? How is power management of multi-core and many-core systems getting validated today?
Power-aware validation is a major concern for designs that are leveraging leading edge power management techniques and if you are working through the challenges, I would love to hear your experiences.
Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. Power management techniques that leverage voltage as a handle are bring extensively used in power sensitive designs. These techniques include: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB). The use of the power management techniques also imply new challenges in validation and testing of designs as new power states are created.
There are some significant new challenges in validation of designs using above mentioned techniques as new power states are created in the design. At physical level, dealing with multiple power supplies and variable power supplies present us with many new verification challenges. Can all of the power issues be addressed at the front-end in the context of simulation-based and formal validation techniques? Or is it unrealistic to even think that any true verification is possible without taking back-end into account? Or is this just one of those over-hyped problems? Some of the largest volume consumer electronic products are using these techniques and how are the companies designing these chips are getting them working in these products? How is power management of multi-core and many-core systems getting validated today?
Power-aware validation is a major concern for designs that are leveraging leading edge power management techniques and if you are working through the challenges, I would love to hear your experiences.
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