Wednesday, September 16, 2009

Strategies for Power Management Verification

In an earlier blog article, we took a look at some of the top power management verification issues. Typical power management verification strategy requires a combination of structural rule-checking, power-aware simulation, and formal validation to address these issues.

In the previous blog article, we discussed the need for power-aware simulation and stressed the fact you have to orchestrate your verification strategy to use structural and formal checking tools to optimize the extent of dynamic simulation needed. In this article, we list various verification strategies for the top verification issues discussed in an earlier article.

In the table listed below, verification strategies are listed as simulation, formal, and structural rule-checking. The notation used here is that “1” implies that the corresponding verification strategy is typically the main strategy for dealing with the issue and “2” being the secondary strategy complementing the main strategy.

Verification Issue Simulation Formal Structural
Reset on Wake Up 1 2*
Power Connectivity 2# 1
Always-on Buffers 1
Domain Isolation 1 2
Power Switching 1$
Power Controller 1 2
Level Shifting 1
Power Sequencing 2 1%
State Retention 1 2
Decaps 1

Table 1: Verification Issues and Strategies


*You can use structural techniques to ensure that proper reset signals are present in the registers for domain under considerations but nothing better than ensuring the reset sequence occurred correctly upon wake up via power-aware simulations.

#You can simulate power connectivity issues if you have power-aware models of cells in the design and have a power-connected netlist. In absence of such a methodology, structural checking to ensure proper connectivity is the only way out. This is a big issue in multi-voltage design and frequent cause of re-spins.

$This is usually done in conjunction with the power connectivity checking to ensure correct power switched signals are reaching their intended destinations.

%Formal is the most secure way of validating properties of power sequencing but this can also be validated via power-aware simulations.

There are other power management verification issues depending upon how you have been bitten in the past but the above mentioned issues generally figure in most low power design verification list. And a coordinated verification strategy involving power-aware simulation, rule-based structural checking, and formal tools is required in your power management verification methodology.

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