Power is a key reason behind the shift in processor design to leverage multi-core architecture as it promises increase in performance without a proportional increase in energy consumption. For an application developer, today’s processors (microprocessors as well as embedded system processors such as cell phone application processors and wireless sensor network nodes) provide multiple cores with a handle on scaling voltage and frequency to manage energy consumed by processors in running various applications. You have to manage both dynamic power (consumed by running applications) and leakage power (to be controlled both in active and standby modes) effectively for these applications.
As you change frequency and voltage, switch cores on and off, and transition among multiple possible modes of operations, you are left with many possibilities to solve the problem under a given performance constraint. It turns out that the best policy to reduce energy is to go slow (operate at lowest possible frequency to achieve application goals) and steady (avoid power state changes) as far as possible.
While this may sound counterintuitive, power efficiency as a result of scaling frequency and voltage has nearly a cubic impact on dynamic power. This is assuming a linear relationship between voltage and frequency. In reality, it may not be an exact linear relation but arguments still hold very well for the typical behavior exhibited. But the time required also increases by the scaling factor leading to a quadratic reduction of dynamic energy. Leakage energy consumed remains nearly the same in the two situations assuming a constant leakage current.
As a result, if you are able to slow things down by a factor of 2, you are looking at nearly 75% reduction in dynamic energy. Assuming dynamic and leakage are equal partners in draining the battery at 65nm, you are looking at nearly 37% overall energy reduction by going slow and steady.
A multi-core processor implemented utilizing dynamic voltage and frequency scaling gives you an option to slow things down provided there is enough parallelism in the application. And such gains are possible in all variations of multi-core architecture utilizing symmetric, asymmetric, and dynamic cores when you can go slow and steady.