"Power-Aware Simulation" here refers to power-aware simulation-based verification. This question has been frequently asked by the designers and becomes an even more important one in the context of potentially increased cost of simulation, with or without recessionary environment.
Those contending that it is not a must-have point to:
• Power-managed designs were being done even when there was no power-aware simulation. The use of rule-based checking addressed most of power related issues and could be custom developed for a design methodology.
• The use of power format brings in a new variable and associated design methodology challenges.
• You could modify the design in a way to see the effects of power shutdowns in a regular simulation context.
• You could modify the design library for simulation to include the effects of power shutdowns. For example, the simulation definition of an AND gate would also include the supply variable VCC and could model the AND gate using the following table: (X implies a 0 or a 1, and Z means a floating value)
A | B | VCC | OUT
1 | 1 | 1 | 1
0 | X | 1 | 0
X | 0 | 1 | 0
X | X | 0 | Z
All of these are valid points but there are some significant issues that are not addressed by these solutions and there are some significant issues which are created by using these solutions. Here are some points for using power-aware simulation:
• There are several power management issues that can only be validated over a few simulation cycles and static checking of the design will not be sufficient. Some of these may indeed get addressed through the use of formal techniques. Ensuring that the proper sequencing of clock gating, power shutdown, isolation, reset and retention occurs is an example pointing to the need of a dynamic method.
• One would like validate a design early in the design cycle and not wait until gate-level simulation. This is an argument against the use of modified library for power-aware simulation. Simulations are lot slower at gate-level leading to higher costs and issues found later in the design cycle will end up costing a lot more through delays in TTM.
• Validations via design modification are effective but introduce another source of error and extra design version management costs. When you are dealing with designs with several power domains, it becomes quickly unmanageable.
• While there are issues related to the use of newly created power formats (i.e., IEEE p1801), it is much better to capture power intent once to coordinate various design tasks. Not only different tools will have a single view of intent, the verification needs to be carried out at various levels of abstraction can now be driven by the same intent.
There is a clear need for power-aware simulation in power-managed designs. While techniques based on design and/or library modifications can do the job, there is an indirect cost to using such methodologies. As power-aware simulation becomes a more mature technology and power-management of designs continue to get more complex, power-aware simulation will become a must-have starting point for chip design creation.