The design and selection of a SoC power delivery network (PDN) presents unique challenges and its design is critical to achieving power consumption goals of the design. This is true when your PDN is external and based on off-the-shelf components as well as when it is being designed on-chip as part of the SoC. This article explores the external situation.
Power architecture of a given power-managed design determines various power modes of that design. Each power mode implies a set of power supply voltages and load current requirements for the PDN. These requirements drive the selection of voltage regulator modules (VRM) that supply the design with appropriate voltage and current levels in different power modes of the design. This process is a lot more challenging that it appears to be.
To begin with, you have the task of establishing target impedances to be met across a range of frequency values for the PDN and then of designing in appropriate decoupling capacitors to meet impedance goals. This is a challenging process in itself but addresses only part of the problem. The selection of appropriate VRMs to supply the design can be equally challenging. Here are some of the factors to consider:
• There are a large number of regulator suppliers such as Texas Instruments, National Semiconductor, Linear Technology, and Analog Devices to name a few.
• The PDN designer needs to carefully look into the switching and linear types of regulators to meet power efficiency and current goals.
• Input and output voltage as well as load current requirements are some of constraints to limit your search
• Power efficiency and consumption goals for the design under consideration must be met.
• Cost of the design places a limit on cost of regulators.
• You can potentially use a hierarchy of regulators to meet these goals.
All of these requirements and given a large number of choices to begin with make this task a challenging one. And it can get more complex when if you bring variable voltages into the picture. It is critical that PDN is done right because an efficient PDN is equivalent to saving a lot effort in optimizing power of the design and the job done well can give you a clear edge in time-to-market with your low power device.